Verified Commit 71f0ebba authored by Ario Amin's avatar Ario Amin

Compiles, will test running on board tomorrow

parent 0659b2d5
MIT License
Copyright (c) 2021 Ario A.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
MIT License
Copyright (c) 2021 Ario A.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
# imxrt1062
This is a bare-metal project for the [Teensy](https://www.pjrc.com/teensy/) 4.0/4.1 board.
The generated HEX file is compatible with the [Teensy Loader](https://www.pjrc.com/teensy/loader.html).
# Credits
Linker files and startup code are based on the [Teensy Core Libraries for Arduino](https://github.com/PaulStoffregen/cores) by Paul Stoffregen.
Initial idea from a fork I started working on yesterdayt, the repo (https://github.com/blazer82/baremetal-blinky.teensy) was a small baremetal example on a teensy 4.0 with a iMX.RT1060
# imxrt1062
This is a bare-metal project for the [Teensy](https://www.pjrc.com/teensy/) 4.0/4.1 board.
The generated HEX file is compatible with the [Teensy Loader](https://www.pjrc.com/teensy/loader.html).
# Credits
Linker files and startup code are based on the [Teensy Core Libraries for Arduino](https://github.com/PaulStoffregen/cores) by Paul Stoffregen.
Initial idea from a fork I started working on yesterdayt, the repo (https://github.com/blazer82/baremetal-blinky.teensy) was a small baremetal example on a teensy 4.0 with a iMX.RT1060
#if DEGUB
#define BL_DEFAULT_PERIPHIAL_DETECT_TIMEOUT 10000
#else
#define BL_DEFAULT_PERIPHIAL_DETECT_TIMEOUT 5000
#endif // DEBUG
// The bootlaoder will chekc for this address in the application vector
#ifndef BL_APP_VECTOR_TABLE_ADDRESS
#define BL_APP_VECTOR_TABLE_ADDRESS (0x10000 + 0x60000000)
#endif
#define BL_PARAMETERS_ADDRESS (0xF000 + 0x60000000)
#define FLASH_VALID_START BL_APP_VECTOR_TABLE_ADDRESS
#if DEGUB
#define BL_DEFAULT_PERIPHIAL_DETECT_TIMEOUT 10000
#else
#define BL_DEFAULT_PERIPHIAL_DETECT_TIMEOUT 5000
#endif // DEBUG
// The bootlaoder will chekc for this address in the application vector
#ifndef BL_APP_VECTOR_TABLE_ADDRESS
#define BL_APP_VECTOR_TABLE_ADDRESS (0x10000 + 0x60000000)
#endif
#define BL_PARAMETERS_ADDRESS (0xF000 + 0x60000000)
#define FLASH_VALID_START BL_APP_VECTOR_TABLE_ADDRESS
#define FLASH_VALID_END (BL_FLEXSPI_AMBA_BASE + 8 * 1024 * 1024)
\ No newline at end of file
This source diff could not be displayed because it is too large. You can view the blob instead.
#ifndef GPIO_HANDLER_H
#define GPIO_HANDLER_H
#include "iomux_controller.h"
typedef enum
{
DR_DATA_REG = 0x0, // RW
GDIR_DIR_REG = 0x4, // RW
PSR_PAD_STATUS_REG = 0x8, // RO
ICR1_INTERRUPT_CONF_REG1 = 0xc, // RW
ICR2_INTERRUPT_CONF_REG2 = 0x10, // RW
IMR_INTERRUPT_MASK_REG = 0x14, // RW
ISR_INTERRUPT_STAT_REG = 0x18, // W1C
EDGE_SEL = 0x1c, // RW
DR_SET = 0x84, // WO
DR_CLEAR = 0x88, // WO
DR_TOGGLE = 0x8c, // WO
} EBaseGPIO;
typedef enum
{
EGPIO_IN = 0x0,
EGPIO_OUT = 0x1
} EGpioGDir;
typedef enum
{
LOW_LVL_SENSITIVITY = 0x0,
HIGH_LVL_SENSITIVITY = 0x1,
RISING_EDGE_SENSITIVITY = 0x2,
FALLING_EDGE_SENSITIVITY = 0x3,
} E_ICRFIELDS_GPIO;
typedef enum
{
EGPIO_INT_DIS = 0x0,
EGPIO_INT_CLR_STAT = 0x1
} EGpioIMR;
/**
* Edge select. When GPIO_EDGE_SEL[n] is set, the GPIO disregards the ICR[n]
* setting, and detects anyedge on the corresponding input signal.
**/
typedef enum
{
EGPIO_EDGE_SET = 0x0,
EGPIO_EDGE_CLR = 0x1
} EGpioEdgeSelect;
typedef enum
{
BYTE,
WORD,
DWORD
} ERegisterSize;
typedef enum
{
GDIR_IN,
GDIR_OUT
} ETypeIO;
// volatile void *void_loc = (volatile void *)0x12345678;
typedef struct {
uint8_t bit_id;
uint8_t value;
vuint32_t * base_addr;
const uint8_t pin;
EBaseGPIO offsets;
ETypeIO io_type;
SStoredMUXDevice * base_mux_device;
} SStoredGPIO; // = {.base_mux_device->mux_mode = ALT5_GPIOx_IOx};
void
init_gpio(SStoredGPIO * gpio_device,
EBaseGPIO gpio_register,
EPadCR pad_group,
EBitMuxPad_DSE dse_opt,
uint8_t ctrl_pos);
/**
* @brief: Set all MUX bits in the correct General Purpose Register (GPR)
**/
void
set_gpr_gdir(SStoredGPIO * gpio_device);
uint8_t
handle_gpio(SStoredGPIO * gpio_device, EBaseGPIO gpio_register);
void
set_icr1(SStoredGPIO * gpio_device, E_ICRFIELDS_GPIO setting);
void
set_icr2(SStoredGPIO * gpio_device, E_ICRFIELDS_GPIO setting);
uint32_t
read_gpio(vuint32_t * gpio_base_ptr, EBaseGPIO gpio_register);
void
set_gpio_muxmode(vuint32_t * gpio_addr, EMuxMode mux_mode);
void
set_gpio_gdir(vuint32_t * gpio_gdir_addr,
ETypeIO io_type,
uint8_t direction_bit);
void
set_gpio_datar(vuint32_t * gpio_dr_set_addr, uint_fast8_t direction_bit);
void
clr_gpio_datar(vuint32_t * gpio_dr_clr, uint_fast8_t direction_bit);
void
tog_gpio_datar(vuint32_t * gpio_dr_tog, uint_fast8_t direction_bit);
void
set_iomuxc_byte(vuint32_t * addr, uint_fast8_t byte);
void
set_iomuxc_word(vuint32_t * addr, uint_fast16_t word);
void
set_iomuxc_dword(vuint32_t * addr, uint_fast32_t dword);
void
flip_selected_gpr(vuint32_t * gpr_iomuxc_gpr);
void
set_iomuxc_gpr(vuint32_t * gpr_iomuxc_gpr, EState set_state);
void
blinky_led_example();
#ifndef GPIO_HANDLER_H
#define GPIO_HANDLER_H
#include "iomux_controller.h"
typedef enum
{
DR_DATA_REG = 0x0, // RW
GDIR_DIR_REG = 0x4, // RW
PSR_PAD_STATUS_REG = 0x8, // RO
ICR1_INTERRUPT_CONF_REG1 = 0xc, // RW
ICR2_INTERRUPT_CONF_REG2 = 0x10, // RW
IMR_INTERRUPT_MASK_REG = 0x14, // RW
ISR_INTERRUPT_STAT_REG = 0x18, // W1C
EDGE_SEL = 0x1c, // RW
DR_SET = 0x84, // WO
DR_CLEAR = 0x88, // WO
DR_TOGGLE = 0x8c, // WO
} EBaseGPIO;
typedef enum
{
EGPIO_IN = 0x0,
EGPIO_OUT = 0x1
} EGpioGDir;
typedef enum
{
LOW_LVL_SENSITIVITY = 0x0,
HIGH_LVL_SENSITIVITY = 0x1,
RISING_EDGE_SENSITIVITY = 0x2,
FALLING_EDGE_SENSITIVITY = 0x3,
} E_ICRFIELDS_GPIO;
typedef enum
{
EGPIO_INT_DIS = 0x0,
EGPIO_INT_CLR_STAT = 0x1
} EGpioIMR;
/**
* Edge select. When GPIO_EDGE_SEL[n] is set, the GPIO disregards the ICR[n]
* setting, and detects anyedge on the corresponding input signal.
**/
typedef enum
{
EGPIO_EDGE_SET = 0x0,
EGPIO_EDGE_CLR = 0x1
} EGpioEdgeSelect;
typedef enum
{
BYTE,
WORD,
DWORD
} ERegisterSize;
typedef enum
{
GDIR_IN,
GDIR_OUT
} ETypeIO;
// volatile void *void_loc = (volatile void *)0x12345678;
typedef struct {
uint8_t bit_id;
uint8_t value;
vuint32_t * base_addr;
const uint8_t pin;
EBaseGPIO offsets;
ETypeIO io_type;
SStoredMUXDevice * base_mux_device;
} SStoredGPIO; // = {.base_mux_device->mux_mode = ALT5_GPIOx_IOx};
void
init_gpio(SStoredGPIO * gpio_device,
EBaseGPIO gpio_register,
EPadCR pad_group,
EBitMuxPad_DSE dse_opt,
uint8_t ctrl_pos);
/**
* @brief: Set all MUX bits in the correct General Purpose Register (GPR)
**/
void
set_gpr_gdir(SStoredGPIO * gpio_device);
uint8_t
handle_gpio(SStoredGPIO * gpio_device, EBaseGPIO gpio_register);
void
set_icr1(SStoredGPIO * gpio_device, E_ICRFIELDS_GPIO setting);
void
set_icr2(SStoredGPIO * gpio_device, E_ICRFIELDS_GPIO setting);
uint32_t
read_gpio(vuint32_t * gpio_base_ptr, EBaseGPIO gpio_register);
void
set_gpio_muxmode(vuint32_t * gpio_addr, EMuxMode mux_mode);
void
set_gpio_gdir(vuint32_t * gpio_gdir_addr,
ETypeIO io_type,
uint8_t direction_bit);
void
set_gpio_datar(vuint32_t * gpio_dr_set_addr, uint_fast8_t direction_bit);
void
clr_gpio_datar(vuint32_t * gpio_dr_clr, uint_fast8_t direction_bit);
void
tog_gpio_datar(vuint32_t * gpio_dr_tog, uint_fast8_t direction_bit);
void
set_iomuxc_byte(vuint32_t * addr, uint_fast8_t byte);
void
set_iomuxc_word(vuint32_t * addr, uint_fast16_t word);
void
set_iomuxc_dword(vuint32_t * addr, uint_fast32_t dword);
void
flip_selected_gpr(vuint32_t * gpr_iomuxc_gpr);
void
set_iomuxc_gpr(vuint32_t * gpr_iomuxc_gpr, EState set_state);
void
blinky_led_example();
#endif
\ No newline at end of file
#ifndef IOMUX_CONTROLLER_H
#define IOMUX_CONTROLLER_H
#include "system_heap.h"
#include "system_memory_map.h"
#ifndef NULL
#define NULL ((void *)0)
#endif
typedef enum
{
ALT0_LCD_DATAx = 0x0, // LCD_DATAx
ALT1_QTIMERx_TIMERx = 0x1, // QTIMERx_TIMERx
ALT2_FLEXPWMx_PWMBx = 0x2, // FLEXPWMx_PWMBx
ALT3_ARM_TRACEx = 0x3, // ARM_TRACEx
ALT4_FLEXIOx_FLEXIOx = 0x4, // FLEXIOx_FLEXIOx
ALT5_GPIOx_IOx = 0x5, // GPIOx_IOx
ALT6_SRC_BOOT_CFGx = 0x6, // SRC_BOOT_CFGx
ALT8_ENET = 0x8 // ENET2_TX_ER
} EMuxMode;
typedef enum
{
SRE = 0x0,
RSRV0 = 0x2,
DSE = 0x3,
SPEED = 0x6,
RSRV1 = 0x8,
ODE = 0xb,
PKE = 0xc,
PUE = 0xd,
PUS = 0xe,
HYS = 0x10,
RSRV2 = 0x11
} EBitFieldOffset_SWPCPGpio;
typedef enum
{
SRE_0_SLOW_SLEW_RATE = 0x0,
SRE_1_FAST_SLEW_RATE = 0x1
} EBitMuxPad_SRE; // Slew Rate Field
typedef enum
{
DSE_0_DISABLED = 0x0,
DSE_1_R0_150O_3_3_V__260O_1_8V = 0x1,
DSE_2_R0_2 = 0x2,
DSE_3_R0_3 = 0x3,
DSE_4_R0_4 = 0x4,
DSE_5_R0_5 = 0x5,
DSE_6_R0_6 = 0x6,
DSE_7_R0_7 = 0x7,
} EBitMuxPad_DSE; // Drive Strength Field
typedef enum
{
SPEED_0_LOW_50MHz = 0x0,
SPEED_1_MID_100MHz = 0x1,
SPEED_2_HI_120MHz = 0x2,
SPEED_3_MAX_200MHz = 0x3,
} EBitMuxPad_SPEED; // Speed Field
typedef enum
{
ODE_0_DRAIN_DISABLED = 0x0,
ODE_1_DRAIN_ENABLED = 0x1
} EBitMuxPad_ODE; // Open Drain Field
typedef enum
{
PKE_0_KEEPER_DISABLED = 0x0,
PKE_1_KEEPER_ENABLED = 0x1
} EBitMuxPad_PKE; // Pull/Keep Enable Field
typedef enum
{
PUE_0_KEEPER = 0x0,
PUE_1_PULL = 0x1
} EBitMuxPad_PUE; // Pull/Keep Select Field
typedef enum
{
PUS_0_100K_OHM_PULL_DOWN = 0x0,
PUS_1_47K_OHM_PULL_UP = 0x1,
PUS_2_100K_OHM_PULL_UP = 0x2,
PUS_3_22K_OHM_PULL_UP = 0x3,
} EBitMuxPad_PUS; // Pull Up/Down Config. Field
typedef enum
{
HYS_0_DISABLED = 0x0,
HYS_1_ENABLED = 0x1
} EBitMuxPad_HYS; // Hysteresis Enable Field
typedef enum
{
RO,
WO,
RW,
W1C
} EAccessRights;
typedef enum
{
LED
} EDeviceType;
typedef enum
{
GPIO_AD_B0,
GPIO_AD_B1,
GPIO_B0,
GPIO_B1,
GPIO_SD_B0,
GPIO_SD_B1
} EPadCR;
typedef union {
EBitMuxPad_SRE slew_rate;
EBitMuxPad_DSE drive_strength;
EBitMuxPad_SPEED speed;
EBitMuxPad_ODE open_drain;
EBitMuxPad_PKE pull_keep_enable;
EBitMuxPad_PUE pull_keep_select;
EBitMuxPad_PUS pull_up_down_conf;
EBitMuxPad_HYS hysteresis_enable;
EMuxMode selected_mux_mode;
} UPadFields;
typedef struct {
vuint32_t * mux_pad_addr;
vuint32_t * pad_pad_addr;
UPadFields current_pad_type;
} SPadContext;
typedef struct {
SPadContext mux_pad_context;
EMuxMode mux_mode;
uint8_t ctrl_pos;
} SStoredMUXDevice;
// 32bit + 32bit + 24bit
// 11 bytes
#define MUXDEVICE_BYTESIZE ((uint8_t)0xc) // an extra byte for good measure
void
init_device_muxmode(SStoredMUXDevice * mux_device,
vuint32_t * sw_mux,
vuint32_t * sw_pad,
EBitMuxPad_DSE dse_opt,
uint8_t ctrl_pos,
EMuxMode mux_mode);
void
set_muxmode(SStoredMUXDevice * mux_device, EMuxMode mux_mode);
#ifndef IOMUX_CONTROLLER_H
#define IOMUX_CONTROLLER_H
#include "system_heap.h"
#include "system_memory_map.h"
#ifndef NULL
#define NULL ((void *)0)
#endif
typedef enum
{
ALT0_LCD_DATAx = 0x0, // LCD_DATAx
ALT1_QTIMERx_TIMERx = 0x1, // QTIMERx_TIMERx
ALT2_FLEXPWMx_PWMBx = 0x2, // FLEXPWMx_PWMBx
ALT3_ARM_TRACEx = 0x3, // ARM_TRACEx
ALT4_FLEXIOx_FLEXIOx = 0x4, // FLEXIOx_FLEXIOx
ALT5_GPIOx_IOx = 0x5, // GPIOx_IOx
ALT6_SRC_BOOT_CFGx = 0x6, // SRC_BOOT_CFGx
ALT8_ENET = 0x8 // ENET2_TX_ER
} EMuxMode;
typedef enum
{
SRE = 0x0,
RSRV0 = 0x2,
DSE = 0x3,
SPEED = 0x6,
RSRV1 = 0x8,
ODE = 0xb,
PKE = 0xc,
PUE = 0xd,
PUS = 0xe,
HYS = 0x10,
RSRV2 = 0x11
} EBitFieldOffset_SWPCPGpio;
typedef enum
{
SRE_0_SLOW_SLEW_RATE = 0x0,
SRE_1_FAST_SLEW_RATE = 0x1
} EBitMuxPad_SRE; // Slew Rate Field
typedef enum
{
DSE_0_DISABLED = 0x0,
DSE_1_R0_150O_3_3_V__260O_1_8V = 0x1,
DSE_2_R0_2 = 0x2,
DSE_3_R0_3 = 0x3,
DSE_4_R0_4 = 0x4,
DSE_5_R0_5 = 0x5,
DSE_6_R0_6 = 0x6,
DSE_7_R0_7 = 0x7,
} EBitMuxPad_DSE; // Drive Strength Field
typedef enum
{
SPEED_0_LOW_50MHz = 0x0,
SPEED_1_MID_100MHz = 0x1,
SPEED_2_HI_120MHz = 0x2,
SPEED_3_MAX_200MHz = 0x3,
} EBitMuxPad_SPEED; // Speed Field
typedef enum
{
ODE_0_DRAIN_DISABLED = 0x0,
ODE_1_DRAIN_ENABLED = 0x1
} EBitMuxPad_ODE; // Open Drain Field
typedef enum
{
PKE_0_KEEPER_DISABLED = 0x0,
PKE_1_KEEPER_ENABLED = 0x1
} EBitMuxPad_PKE; // Pull/Keep Enable Field
typedef enum
{
PUE_0_KEEPER = 0x0,
PUE_1_PULL = 0x1
} EBitMuxPad_PUE; // Pull/Keep Select Field
typedef enum
{
PUS_0_100K_OHM_PULL_DOWN = 0x0,
PUS_1_47K_OHM_PULL_UP = 0x1,
PUS_2_100K_OHM_PULL_UP = 0x2,
PUS_3_22K_OHM_PULL_UP = 0x3,
} EBitMuxPad_PUS; // Pull Up/Down Config. Field
typedef enum
{
HYS_0_DISABLED = 0x0,
HYS_1_ENABLED = 0x1
} EBitMuxPad_HYS; // Hysteresis Enable Field
typedef enum
{
RO,
WO,
RW,
W1C
} EAccessRights;
typedef enum
{
LED
} EDeviceType;
typedef enum
{
GPIO_AD_B0,
GPIO_AD_B1,
GPIO_B0,
GPIO_B1,
GPIO_SD_B0,
GPIO_SD_B1
} EPadCR;
typedef union {
EBitMuxPad_SRE slew_rate;
EBitMuxPad_DSE drive_strength;
EBitMuxPad_SPEED speed;
EBitMuxPad_ODE open_drain;
EBitMuxPad_PKE pull_keep_enable;
EBitMuxPad_PUE pull_keep_select;
EBitMuxPad_PUS pull_up_down_conf;
EBitMuxPad_HYS hysteresis_enable;
EMuxMode selected_mux_mode;
} UPadFields;
typedef struct {
vuint32_t * mux_pad_addr;
vuint32_t * pad_pad_addr;
UPadFields current_pad_type;
} SPadContext;
typedef struct {
SPadContext mux_pad_context;
EMuxMode mux_mode;
uint8_t ctrl_pos;
} SStoredMUXDevice;
// 32bit + 32bit + 24bit
// 11 bytes
#define MUXDEVICE_BYTESIZE ((uint8_t)0xc) // an extra byte for good measure
void
init_device_muxmode(SStoredMUXDevice * mux_device,
vuint32_t * sw_mux,
vuint32_t * sw_pad,
EBitMuxPad_DSE dse_opt,
uint8_t ctrl_pos,
EMuxMode mux_mode);
void
set_muxmode(SStoredMUXDevice * mux_device, EMuxMode mux_mode);
#endif // IOMUX_CONTROLLER_H
\ No newline at end of file
#ifndef IOMUX_MANAGER_H
#define IOMUX_MANAGER_H
#include "gpio_handler.h"
// #include "lcdif_handler.h"
// #include "qtimer_handler.h"
// #include "flexpwm_handler.h"
// #include "armtrace_handler.h"
// #include "flexio_handler.h"
// #include "srcboot_handler.h"
// #include "enet_handler.h"
typedef union {
// SStoredDEVICE _device;
// SStoredDEVICE _device;
// SStoredDEVICE _device;
// SStoredDEVICE _device;
// SStoredDEVICE _device;
SStoredGPIO gpio_device;
// SStoredDEVICE _device;